With rapid development of semiconductor fabrication technology, in order to achieve faster computing speed, greater data storage capacity and more features, semiconductor chips are being developed toward a higher degree of integration. One of the developments is packaging using through silicon via (TSV) technology. That is, a TSV runs through an entire semiconductor substrate to form electrical conduction path between stacked chips, thus realizing electrical connections between different chips. In contrast with conventional wire bonding technology, packaging using the TSV technology can accomplish maximum density and minimum sizes for chips stacked in three-dimension directions, and can greatly improve chip speed and performance at low power consumption.
In existing technology, usually input/output (I/O) ports of an integrated circuit (IC) are electrically connected to electrostatic discharge (ESD) protection structures in order to protect the IC from being affected by electrostatic discharge. High voltages may be generated during an electrostatic discharge and may reach hundreds or even thousands of volts. In order to prevent the IC from being destroyed by burning, all of the ESD protection structures formed by existing technology take up a large chip area.
When using the wire bonding technology for packaging, an entire IC is located in an integral chip and only a limited number of I/O ports need to be electrically connected to the ESD protection structures. However, when using the TSV technology for packaging, an IC is divided and formed on different chips and the I/O ports of each stacked chip need to be electrically connected to the ESD protection structures. Thus, the chip area occupied by the ESD protection structures is multiplied.
At the same time, a material that fills the TSV is copper. When temperature changes, because copper and the semiconductor substrate have different coefficients of thermal expansion, the TSV tends to generate stress in the surrounding semiconductor substrate. As a result, electrical parameters of semiconductor devices formed around the TSV can change and be difficult to control. Therefore, isolation regions need to be formed around the TSV, and there should not be semiconductor devices formed in the isolation regions. Because the isolation regions can also take up a large portion of the chip area, overall area utilization of the chip is not satisfied.